Battery-operated apparatuses such as mobile telephones, laptops or PDAs often require different supply voltages for their individual circuits. For this purpose, they use voltage regulators that transform the voltage supplied by the battery into the required supply voltage. The output voltage of such a voltage regulator is often close to the battery voltage. For such cases, voltage regulators are usually realized with MOS transistors as output stages, because these have the advantage over bipolar transistors that they can also realize small voltage differences between an input voltage and an output voltage. In addition, compared with bipolar transistors, they operate without any power and require no base currents. In the concrete case of the embodiment, however, problems may arise with MOS transistors if a potential applied to the drain terminal changes unfavorably.
Such a case is shown schematically in FIG. 3. The latter shows a PMOS field-effect transistor having a source terminal 2, a drain terminal 1 and also a gate terminal 3. The PMOS transistor is formed in an n-doped well having a plurality of heavily n-doped regions n+ that form the contacts for a bulk terminal 4. The potential VS is present at the source terminal 2 of the PMOS transistor and the potential VD is present at the drain terminal 1 of the transistor. A connection between the source terminal 2 and the bulk terminal 4 pulls the n-type well of the PMOS transistor to the source potential VS.
If the potential VD exceeds the potential VS by the value of a threshold voltage, then the pn junctions act as forward-biased substrate diodes BD. A parasitic vertical transistor VT and a parasitic lateral transistor LT are formed, which may bring about an undesirable current flow and, in the worst case, destroy a circuit connected to the drain terminal. In order to avoid damage to an integrated circuit as a result of a current flow in the opposite direction, the prior art makes use of the following solutions.
FIG. 4A shows a pnp bipolar transistor as an output stage. Its base-emitter diode inhibits the current path to the supply potential at the input S if the potential at the output D lies above the potential at the input S. However, such a design requires a base current and furthermore exhibits a relatively high saturation voltage.
In FIG. 4B, a Schottky diode SD is connected between the drain terminal of a PMOS transistor and an output D.
Said Schottky diode inhibits a current if it is biased in the opposite direction, that is to say the potential at the output D rises above the input potential at S. A disadvantage of this embodiment is the voltage drop across the Schottky diode, which thus defines a minimum voltage difference between input S and D.
FIG. 4C shows a known concept having a second PMOS transistor ST that operates in the opposite direction and is in a conducting state only in the normal operating mode. This likewise prevents a current in the opposite direction. However, a small difference between the potential at the input S and the potential at the output D is likewise impossible in the case of this circuit. The concept known from FIG. 4C is suitable rather for high-voltage applications in which power transistors are used.